1. Technical Field
The present invention relates in general to recording and visualizing the operation of systems under test, and in particular, to methods, systems and program products for recording and visualizing the operation over time of a simulated system or module in which traces of particular signals are annotated with control program information.
2. Description of the Related Art
In a typical digital design process, verifying the logical correctness of a digital design and debugging the design (if necessary) are important steps of the design process performed prior to developing a circuit layout. Although it is certainly possible to test a digital design by actually building the digital design, digital designs, particularly those implemented by integrated circuitry, are typically verified and debugged by simulating the digital design on a computer, due in part to the time and expense required for integrated circuit fabrication.
In a typical automated design process, a circuit designer enters into an electronic computer-aided design (ECAD) system a high-level description of the digital design to be simulated utilizing a hardware description language (HDL), such as VHDL, thus producing a digital representation of the various circuit blocks and their interconnections. In the digital representation, the overall circuit design is frequently divided into smaller parts, hereinafter referred to as design entities, which are individually designed, often by different designers, and then combined in a hierarchical manner to create an overall model. This hierarchical design technique is very useful in managing the enormous complexity of the overall design and facilitates error detection during simulation.
The ECAD system compiles the digital representation of the design into a simulation model having a format best suited for simulation. A simulator then exercises the simulation model to detect logical errors in the digital design.
A simulator is typically a software tool that operates on the simulation model by applying a list of input stimuli representing inputs of the digital system. The simulator generates a numerical representation of the response of the system to the input stimuli, which response may then either be viewed on a display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. One common tool that is utilized to visualize the operation of a simulated system is a trace viewer (sometimes referred to as an All Events Trace (AET) viewer) that presents the states of various signals of interest within the system as they vary over time.
In current simulation environments, it is possible for a control program that controls the operation of the simulator to call API functions within the simulator to read and alter values within the simulation model. The present invention appreciates that when values are modified within a model during a simulation run in this manner, a designer can become confused regarding the true operation of the system. For example, logic within the design under test may have driven a signal to a particular value, while the control program has, in fact, driven the signal of interest to a different value. Because of these differences in values, a designer can waste significant time in debugging the trace based upon what are thought to be errors and which are, in fact, external manipulations of system state.